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ARINC 818 IP (transceiver) core pin diagram
ARINC 818 IP (transceiver) core. See Datasheet for further details.

IP Core

Great River's ARINC 818 IP Core provides an easy way to implement ARINC 818–compliant interfaces in Xilinx and Altera PLDs. The core can achieve ARINC 818 interfaces up to 12.75 Gb/s. It can be used for transmit-only, receive-only, or transmit-and-receive applications.

The core has many flexible compile-time settings, allowing for various link speeds, line segmentations, and line-synchronization methods. It can be configured for various resolutions and pixel packing methods. Ancillary data can use default values set at compile time, or data can be updated in real time via register interface.


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Transmitter and receiver

ARINC 818 transmitter block diagram
The transmitter has a simple interface where native Vsync, Hsync, and pixel clocks can be used. Out-going ARINC 818 frames are governed by this input timing. Internal FIFOs allow writing of continuous line data without hold off; therefore, the core can be tied directly to pixel buses with various timings (such as VESA timings). The core supports various color input formats (up to 32-bit RGBA) and monochrome formats (up to 16 bits). Internal pixel packing logic can be configured to compress data prior to transmission.

ARINC 818 receiver block diagram
The receiver is configurable for unpacking pixel data in several formats. The PLD interface is a 32-bit wide data bus with a simple "data valid" signal. The core has internal receiver FIFOs so that the pixel clock rate can be set by the user.
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